arrays - 无法在 Verilog 中创建“真实”类型数组

Question

我尝试在 Icarus Verilog 中以下列方式创建一个“真实”类型的值数组：

parameter width = 10;
shortreal b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181};

给出以下错误：

error: Cannot assign to array b. Did you forget a word index?

我浏览了 icarus verilog src 代码错误消息，对此的解释是“特殊情况：l 值是整个内存或数组切片”。这实际上是 l 值的错误。通过注意索引计数是否小于数组维度（未打包）来检测情况”，我认为这意味着数组索引大小与声明的大小不同[width-1:0]，如果我理解的话，这是不正确的。

我也试过：

parameter width = 10;
parameter [32:0] b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181};

但没有任何成功。

使用带有-g2012标志的 Icarus Verilog（用于 SV 支持）

Answer 1

如果填充整个数组，则仅使用所谓的数组连接是合法的。您的数组有 10 个元素，但右侧只有 9 个：

parameter width = 10;
shortreal b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181,0.0181};