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我需要使用 generate for 循环来复制一些具有接口的模块实例，并且我遇到了一个详细说明问题。我将尝试用这个例子来说明问题。我已经声明了一个简单的接口，然后我在下面创建了一个分层设计，顶部模块跟随接口，然后向下。当我使用 ncverilog 运行此设计时，出现以下错误：

.write (test_intf.w), | ncelab: *E,CUIOAI (./test_generate_interface.sv,105|21): 通过生成或数组实例的非法接口端口连接 (test_wrap.genblk1[0].test.test_intf.w) 。test_intf.w 写，| ncelab: *E,CUIMBC (./test_generate_interface.sv,116|18)：必须连接接口端口声明 (test_wrap.genblk1[0].test.test_intf_top.write_read)。.read (test_intf.r)

开始代码----------------

interface test_intf
    #(parameter W = 32)
();

logic [(W-1):0] wdata;
logic [(W-1):0] rdata;
logic read;
logic write;

modport w
(
  input write,
  input wdata
);


modport r
(
  input read,
  output rdata
);

endinterface

module test_wrap
#(
  parameter NUM = 5,
  parameter W   = 32
  )
(
 input clk,
 input rst,
 input [(NUM-1):0] [(W-1):0]  wdata,
 input [(NUM-1):0]            write,
 input [(NUM-1):0]            read,
 output [(NUM-1):0] [(W-1):0] rdata
 );

 genvar v;

  generate
   for (v = 0; v < NUM; v++)
     test
     #(.W(W))
     test
     (
      .clk(clk),
      .rst(rst),
      .read(read [v]),
      .write(write [v]),
      .wdata(wdata [v]),
      .rdata(rdata [v])
     );

  endgenerate
 endmodule

module test
#(parameter W = 32)
(
 input            clk,
 input            rst,
 input            read,
 input            write,
 input  [(W-1):0] wdata,
 output [(W-1):0] rdata
 );

test_intf 
#(.W(W))
test_intf
();

assign test_intf.write  = write;
assign test_intf.wdata  = wdata;
assign test_intf.read   = read;
assign rdata  = test_intf.rdata;

test_intf_top
#(.W (W)) 
test_intf_top
(
 .clk  (clk),
 .rst  (rst),
 .test_intf(test_intf)
 );

endmodule

module test_intf_top
#(parameter W = 32)
(
 input clk,
 input rst,
 test_intf test_intf
 );


 write_read
  #(.W(W))
  write_read
  (
   .clk (clk),
   .rst(rst),
   .write (test_intf.w),
   .read (test_intf.r)
  );

 endmodule

 module write_read
 #(parameter W = 32)
 (
  input clk, 
  input rst,
  test_intf.w write,
  test_intf.r read
  );

reg [(W-1):0] counter;

always_ff @(posedge clk or negedge rst)
  if (~rst)
    begin
      counter <= '0;
    end
  else
    begin
      if (write.write)
        counter <= write.wdata;
      else if (read.read)
        read.rdata <= counter;
      else
        counter <= counter + 1;
    end
endmodule
4

1 回答 1

0

我可以用不同的模拟器在EDAplayground上复制你的问题。您将接口实例命名为与其声明名称相同，这会使模拟器感到困惑。具体来说，模拟器看到任何用法test_intf.w并test_intf.r引用 modeport int 的定义定义test_intf；不使用您想要的相同名称进行实例化。

建议您保持名称唯一。通过更改实例名称，我能够让它编译和运行而不会出错。

//...

module test_wrap
#(
  parameter NUM = 5,
  parameter W   = 32
  )
(
 input clk,
 input rst,
 input [(NUM-1):0] [(W-1):0]  wdata,
 input [(NUM-1):0]            write,
 input [(NUM-1):0]            read,
 output [(NUM-1):0] [(W-1):0] rdata
 );

 genvar v;

  generate
   for (v = 0; v < NUM; v++)
     test
     #(.W(W))
     test_inst // rename instname test to test_inst
     (
      .clk(clk),
      .rst(rst),
      .read(read [v]),
      .write(write [v]),
      .wdata(wdata [v]),
      .rdata(rdata [v])
     );

  endgenerate
endmodule

module test
#(parameter W = 32)
(
 input            clk,
 input            rst,
 input            read,
 input            write,
 input  [(W-1):0] wdata,
 output [(W-1):0] rdata
 );

test_intf 
#(.W(W))
test_if // rename instname test_intf to test_if
();

assign test_if.write  = write; // rename instname test_intf to test_if
assign test_if.wdata  = wdata; // rename instname test_intf to test_if
assign test_if.read   = read; // rename instname test_intf to test_if
assign rdata  = test_if.rdata; // rename instname test_intf to test_if

test_intf_top
#(.W (W)) 
test_if_top // rename instname test_intf_top to test_if_top
(
 .clk  (clk),
 .rst  (rst),
 .test_if(test_if) // rename portname/instname test_intf to test_if
 );

endmodule

module test_intf_top
#(parameter W = 32)
(
 input clk,
 input rst,
 test_intf test_if // rename portname/instname test_intf to test_if
 );


 write_read
  #(.W(W))
  write_read
  (
   .clk (clk),
   .rst(rst),
   .write (test_if.w), // rename instname test_intf to test_if
   .read (test_if.r) // rename instname test_intf to test_if
  );

 endmodule

 // ...
于 2018-09-19T17:03:33.797 回答