我目前有一个非常非常基本的 DDS 内核(?),带有一个计数器、调谐字和正弦 LUT,它输出 16 位值以与 DAC 的正弦值相关。我使用的是Nexys 4 DDR 板,我的DAC是专为 FPGA 设计的外围模块。如果它是一个 16 位 DAC,为什么它有 6 个引脚,其中只有 4 个用于数据?我应该如何将二进制信息从我的 16 位生成的 sin 值发送到 DAC,以便 DAC 成功转换?
这是我的代码(我知道它的初级,请原谅错误,一旦我正确地知道如何与 DAC 交互,我会解决它们!)
module sin_LUT(
input clk,
input [0:3] M,
input rst,
output reg [16:0] data_out,
output reg [32:0]test
);
//counter
//declaring constant
integer i;
integer int_M;
always @(M)
int_M = M;
always @(posedge(clk))
begin
if (rst)
i <= 0;
else if (i >= 29)
i <= 0;
else
i <= i + M;
end
//testing purposes
always @(i)
test = i;
//sine LUT
always @(i) begin
case (i)
0: data_out = 16'D32768;
1: data_out = 16'D39812;
2: data_out = 16'D46526;
3: data_out = 16'D52598;
4: data_out = 16'D57742;
5: data_out = 16'D61718;
6: data_out = 16'D64341;
7: data_out = 16'D65487;
8: data_out = 16'D65103;
9: data_out = 16'D63208;
10: data_out = 16'D59889;
11: data_out = 16'D55302;
12: data_out = 16'D49661;
13: data_out = 16'D43230;
14: data_out = 16'D36310;
15: data_out = 16'D29225;
16: data_out = 16'D22305;
17: data_out = 16'D15874;
18: data_out = 16'D10233;
19: data_out = 16'D5646;
20: data_out = 16'D2327;
21: data_out = 16'D432;
22: data_out = 16'D48;
23: data_out = 16'D1194;
24: data_out = 16'D3817;
25: data_out = 16'D7793;
26: data_out = 16'D12937;
27: data_out = 16'D19009;
28: data_out = 16'D25723;
29: data_out = 16'D32768;
default: data_out = 16'b0000111100001111;
endcase
end
endmodule