vhdl - 此处只能声明 SHARED 变量

Question

我需要你的帮助来解决这个问题：

-Line 34. Only SHARED variables can be declared here
-Line 35. Only SHARED variables can be declared here
-Line 36. parse error, unexpected IDENTIFIER

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Managementsystem is
            port( e     :  in    std_logic;
                    s       :  out   std_logic_vector (0 to 5)
                );
end Managementsystem;

architecture Managment_Archi of Managementsystem is
    type State is (st1,st2,st3,st4,st5,st6,st7,st8);
    signal w:State;
    variable Ppv, Pwind, Pl, SOC, SOCmin, SOCmax : integer range 0 to 1000000;
    variable x, y, z, a, b : integer range 0 to 1000000;
    x <= (Ppv > Pl);
    y <= (Pwind > Pl);
    z <= ((Ppv + Pwind) > Pl);
    a <= (SOC > SOCmin);
    b <= (SOC < SOCmax);
begin
    process (e,w)
    begin
            case w is
            when st1 =>
            if e = z then w <= st5 ;
            elsif e = y then w <= st1 ;
            elsif e = x then w <= st3 ;
            elsif e = (not (z) and a) then w <= st7;
            else w <= st1;
            end if;
            end case;
    end process;                    
    --with w select
        s <= "010010" when st1;
        --s <= "011010" when st2;
        --s <= "100001" when st3;
        --s <= "101001" when st4;
        --s <= "110000" when st5;
        --s <= "110100" when st6;
        --s <= "111000" when st7; -- décharge
        --s <= "111000" when st8; -- charge
end Managment_Archi;